QORC-SDK GPIO HAL

This file contains macros, structures and APIs to mainpulate the GPIOs in the EOS S3.

This file contains API implementation to mainpulate the GPIOs in the EOS S3.

Defines

GPIO_0: GPIO index 0.

GPIO_1: GPIO index 1.

GPIO_2: GPIO index 3.

GPIO_3: GPIO index 3.

GPIO_4: GPIO index 4.

GPIO_5: GPIO index 5.

GPIO_6: GPIO index 6.

GPIO_7: GPIO index 7.

PAD_COUNT

S_INTR_SEL_BASE

Typedefs

typedef struct __GPIOCfgTypeDef GPIOCfgTypeDef: GPIO Configuration Structure definition.

Enums

enum GPIO_INTR_TYPE

Values:

enumerator LEVEL_TRIGGERED

enumerator EDGE_TRIGGERED

enum GPIO_POL_TYPE

Values:

enumerator FALL_LOW

enumerator RISE_HIGH

Functions

void HAL_GPIO_Read(uint8_t ucGpioIndex, uint8_t *ucGpioVal)

GPIO read function to read pad status. Before using this function given pad needs to be initalized.

Parameters:

ucGpioIndex – - GPIO index that needs to be read.
*ucGpioVal – - GPIO status read, return value pointer.

Returns:

None

void HAL_GPIO_Write(uint8_t ucGpioIndex, uint8_t ucGpioVal)

GPIO write function to write to pad . Before using this function given pad needs to be initalized.

Parameters:

ucGpioIndex – - GPIO index that needs to be written.
ucGpioVal – - GPIO status that needs to be written.

Returns:

None

HAL_StatusTypeDef HAL_GPIO_IntrCfg(GPIOCfgTypeDef *hGpioCfg)

Function to write to configure pad as GPIO interrupt. PAD initialization will be done based on the parameter passed. GPIO Interrupt Usage :

EDGE TRIGGERED Set the interrupt type as Edge Triggered and polarity as Rising/Falling Edge. At the Rising/Falling Edge, interrupt will be generated which is reflected in INTR_CTRL->GPIO_INTR register (0x40004800) This interrupt can be cleared by writing 1 to the corresponding bit in INTR_CTRL->GPIO_INTR register.

LEVEL TRIGGERED Set the interrupt type as Level Triggered and polarity as Active High/Low. Depending on the polarity , interrupt will be generated. The value of the GPIO is reflected in GPIO_INTR_RAW (0x40004804) regardless of the polarity. Check the corresponding bit of the GPIO_INTR_RAW for the desired value and proceed with the ISR. This interupt needs to be cleared from Source of the interrupt. For example, if the GPIO_0 is configured as LEVEL TRIGGERED Active Low interrupt, then the interrupt can be cleared by writng 1 (pulled HIGH) to GPIO_0 by Source (AP) (M4 can disable the interrupt and convey the AP to clear the interrupt(by setting the line as High) and re-enable the interrupt once AP clears the interrupt) (* depending on the usecase). Note : In case of level triggered, interrupt will NOT be reflected in INTR_CTRL->GPIO_INTR register (0x40004800).

Parameters:: hGpioCfg – - pointer to GPIO configuration structure.
Returns:: HAL_StatusTypeDef status of GPIO interrupt configuration operation

void configure_s3_gpio_interrupts(GPIOCfgTypeDef *p_table, int nitems)

Configures PADs as interrupts using given configurations in p_table Also, initializes PADs using the configurations provided in p_table

Parameters:

p_table – table of GPIOCfgTypeDef structures
nitems – number of GPIOCfgTypeDef structures to configure

Returns:

None

struct __GPIOCfgTypeDef

#include <eoss3_hal_gpio.h>

GPIO Configuration Structure definition.

Public Members

uint8_t ucGpioNum

uint16_t usPadNum: GPIO Num : 0 -7

uint32_t ucFunc: PAD Num/Pin num corresponding to GPIO Num : 0-45 (used for PAD config)

uint8_t ucPull: Pad function selection (used for PAD config)

GPIO_INTR_TYPE intr_type: Pad Pull up config (used for PAD config)

GPIO_POL_TYPE pol_type: GPIO Interrupt type